In computer systems today, ranging from PC's to mainframes, there are many chips that operate at different clock frequencies. For example the CPU chip usually operates at 2.times., 3.times. or 4.times. the frequency of the other chips that communicate to it. The reason for this is that the communication between chips on a card or board can not support the faster cycle time that the CPU chip can operate internally. Usually a PLL (Phase Locked Loop) or some other frequency multiplication circuit is used to generate the faster frequency clock from the slower system clock that is distributed to each chip on the board or card. In order for these chips to synchronously communicate with each other, they MUST know the cycle time relationship between their clocks and the clocks on the chips that they are communicating to. Simply stated, the problem Is how do chips that operate at different clock frequencies that are multiplies of each other, know the cycle time relationship between their clocks?